tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 27

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

May 2001
3 Pin Information
3.3.9 Framer PLL
The DS1/E1 framer has a phase-locked loop that may be used to generate a transmit line clock at 1.544 MHz or
2.048 MHz. The reference signal for this PLL may be chosen from a number of possible sources, all typically syn-
chronized to the system clock (CHI transmit/receive clock for example.) In order to ensure reliable performance
,this PLL has its own isolated power pins. The PLL also has a number of test control pins that are used for factory
testing only.
The PLL is active when framer bit PLL_BYPAS = 0. When PLL_BYPAS = 1, the PLL is bypassed and an external
clock at the system interface is used as the line clock. An example would be when the framers are programmed for
a CHI interface at 2.048 MHz and the frames are programmed for E1, the PLL may be bypassed and the CHI sys-
tem clock may be used as the line clock.
Table 13. Framer PLL
Agere Systems Inc.
AD22
AD23
AD24
AE23
AF23
AB21
AF24
AE24
Pin
MODE2_PLL
MODE0_PLL
MODE1_PLL
CLKIN_PLL
VDDD_PLL
VDDS_PLL
VSSA_PLL
VSSS_PLL
Symbol
(continued)
Type
VDD
VDD
VSS
VSS
—
—
—
—
Pull down
Pull down
Pull down
I/O
I/O
—
—
—
—
I
I
I
Digital VDD for PLL.
Analog VDD for PLL.
Analog VSS for PLL.
Digital VSS for PLL.
Clock In PLL. Phase locked-loop reference clock input. Fre-
quency should be consistent with the MODE_PLL pins in the
PLL Mode1 table below. A 1.544 MHz clock for DS1 transmit
outputs is generated synchronous to this clock.
PLL Mode 2. Control bit that should be tied to the appropriate
state depending on the frequency of CLKIN_PLL consistent
with the PLL Mode1 table below. This pin is also used during
factory testing as an output.
PLL Mode 0. PLL control input 0.
PLL Mode 1. PLL control input 1. The PLL mode inputs should
be hardwired to the logic levels shown in the table below,
depending on the frequency of the reference supplied to
CLKIN_PLL.
Mode2
0
0
0
0
1
1
1
1
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Mode1
0
0
1
1
0
0
1
1
Description
Mode0
0
1
0
1
0
1
0
1
26.624 MHz
16.348 MHz
CLKIN_PLL
51.84 MHz
19.44 MHz
8.194 MHz
4.096 MHz
2.048 MHz
Reserved
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