tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 478

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

TMXF28155/51 Super Mapper
Preliminary Data Sheet
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
May 2001
21 28-Channel Framer Block Functional Description
(continued)
Table of Contents
(continued)
Tables
Page
Table 576. Frame Alignment Criteria ................................................................................................................... 489
Table 577. Receive Signaling Link Registers 0—31 Bit Description ................................................................... 491
Table 578. Receive Signaling Link Registers 0—31 G-Bit and F-Bit Description ................................................ 491
Table 579. Receive Signaling Link Registers 0—31 DS1/CEPT/CMI Data ......................................................... 493
Table 580. Receive Signaling Link Registers 0—31 Expected Data ................................................................... 494
Table 581. Signaling Receive Global Register 3, Bit Definition ........................................................................... 495
Table 582. Transmit Signaling Link Registers 0—31 Bit Description .................................................................. 498
Table 583. Transmit Signaling Link Registers 0—31 G-Bit and F-Bit Description ............................................... 498
Table 584. Transmit Signaling Link Registers 0—31 DS1/CEPT/CMI Data ........................................................ 499
Table 585. Transmit Signaling Link Registers 0—31 Expected Data .................................................................. 500
Table 586. Performance Monitor Functional Descriptions ................................................................................... 503
Table 587. Performance Report Message Format .............................................................................................. 507
Table 588. Performance Report Message Field Definition .................................................................................. 507
Table 589. Shared Rx Stack Format for SLC-96 Frames .................................................................................... 509
Table 590. Shared Rx FDL Stack Format for DDS Frames ................................................................................ 510
Table 591. Shared Rx Stack Format for CEPT Frames ...................................................................................... 510
Table 592. Shared Tx FDL Stack Format for SLC-96 Frames ............................................................................ 513
Table 593. Shared Tx FDL Stack Format for DDS Frames ................................................................................. 514
Table 594. Shared Tx Stack Format for CEPT Frame ........................................................................................ 515
Table 595. HDLC Frame Format ......................................................................................................................... 517
Table 596. Performance Report Message Structure ........................................................................................... 521
Table 597. Clock Mode Programming for PLL Mode Device Pins ...................................................................... 522
Table 598. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames ..................................... 529
Table 599. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels .............................. 530
Table 600. Associated Signaling Mode CHI 2-Byte Time-Slot format for CEPT ................................................. 530
Table 601. Programming Values for FRM_TOFF[2:0] and FRM_ROFF[2:0] when FRM_CMS = 0 .................... 530
Table 602. Programming Values for FRM_TOFF[2:0] when FRM_CMS = 1 ...................................................... 530
Table 603. Programming Values for FRM_ROFF[2:0] when FRM_CMS = 1 ...................................................... 530
Table 604. Parallel System Bus Interface Time-Slot Arrangement for DS1 ........................................................ 534
Table 605. Parallel System Bus Interface Time-Slot Arrangement for E1 ........................................................... 535
Table 606. PSB System I/O Definition ................................................................................................................. 535
Table 607. Serial ID ............................................................................................................................................. 538
Table 608. Current Number of Global and per Link/Channel Registers for Each Block ...................................... 540
Table 609. Framer Addressing Map for the Global and Per Link/Channel Registers of the Superframer ........... 541
478
Agere Systems Inc.