tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 521

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
21 28-Channel Framer Block Functional Description
Table 596. Performance Report Message Structure
In
1 to force nonshared flags), SAPI = 001110, C/R is programmable, EA = 0 in octet 2 and 1 in octet 3, TEI =
0000000, Control = 00000011. Octets 5 and 6 contain the most recent data received from the performance monitor
(except U1, U2, R = 0 always). Octets 7 and 8 contain the same data from the previous second. Octets 9 and 10
contain data from the second before that (antepenultimate second) and octets 11 and 12 contain data for the sec-
ond before that. The FCS is automatically generated by the HDLC.
The data normally received from the performance monitor will be initialized to all zeros.
Transmit HDLC data is loaded into the channel transmit FIFO (TFIFO) via the Tx HDLC channel data bits
FRM_HTDATA[7:0]
each frame is marked by writing the Tx HDLC FRM_HTFUNC[1:0]
transmit HDLC channel count register indicates how many additional bytes can be added to the Tx HDLC FIFO.
The transmitter empty (Tx HDLC FRM_HTTHRSH
ister when the TFIFO is below the number of bytes specified in the threshold registers.
A Tx HDLC FRM_HTDONE interrupt occurs for each HDLC frame completed.
In HDLC mode, an Tx HDLC FRM_HTUND
no interrupt indicated for a transmitter overrun that is writing more data than empty spaces exist. Overrunning
transmitter data is ignored which results in missing data in the frame.
Agere Systems Inc.
Octet Number
Any channel can be programmed to run for any combination of bits for any one time slot of either odd or even (or
both) frame numbers of any link.
A local loopback is supported. (From transmit FIFO through the HDLC back to the receive FIFO.)
The PRM data is received from the framer performance monitoring block approximately once per second per
link. If the link is enabled to send PRM data, then the PRM packet will be sent as the next packet on that link. The
PRM packet contains data for the current and three previous seconds. The format of the PRM packet is shown in
Table 587, Performance Report Message Format on page
Table
13—14
10
11
12
15
596, the flags (octet 1 and 15) are normal HDLC flags (note that the CFLAGS bit must be programmed to
1
2
3
4
5
6
7
8
9
(Table
PRM B7
G3
FE
G3
FE
G3
FE
G3
FE
438). Multiframes can be placed in the Tx HDLC FIFO. In HDLC mode, the final byte of
PRM B6
SE
SE
SE
SE
LV
LV
LV
LV
PRM B5
(Table
G4
G4
G4
G4
LB
LB
LB
LB
SAPI
436) interrupt is generated if the transmitter underruns. There is
(Table
PRM B4
TEI
U1
G1
U1
G1
U1
G1
U1
G1
436)) interrupt bit is set in the HDLC interrupt status reg-
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Control
FLAG
FLAG
FCS
507.
PRM B3
(Table
U2
U2
U2
U2
R
R
R
R
(continued)
438) bits to the appropriate value. The
PRM B2
TMXF28155/51 Super Mapper
G5
G2
G5
G2
G5
G2
G5
G2
PRM B1
C/R
Nm
Nm
Nm
Nm
SL
SL
SL
SL
PRM B0
EA
EA
G6
G6
G6
G6
NI
NI
NI
NI
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