ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 101

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

ST72324Bxx
10.4.4
Note:
Note:
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an Overrun condition (see
(OVR) on page
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (see
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge
Figure 54
The diagram may be interpreted as a master or slave timing diagram where the SCK, MISO
and MOSI pins are directly connected between the master and the slave device.
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Figure 54. Data clock timing diagram
1. This figure should not be used as a replacement for parametric information. Refer to the Electrical
Characteristics chapter.
Figure
(from master)
(from slave)
MISO
(from slave)
SCK
(CPOL = 0)
MOSI
Capture strobe
(CPOL = 1)
SCK
(CPOL = 0)
(from master)
Capture strobe
(CPOL = 1)
(to slave)
SCK
MISO
MOSI
SCK
SS
(to slave)
SS
shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
102).
54).
MSB
MSB
MSB
MSB
Bit 6
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
(1)
CPHA = 0
CPHA = 1
Bit 4
Bit 4
Bit 4
Bit 4
Bit3
Bit3
Bit3
Bit3
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
On-chip peripherals
LSB
LSB
LSB
Overrun condition
LSB
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