ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 39

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

ST72324Bxx
6.6
6.6.1
SI registers
System integrity (SI) control/status register (SICSR)
Table 12.
Table 13.
SICSR
3:1
Bit
7
6
5
4
0
Res
7
-
WDGRF
LVDRF
AVDIE
Name
AVDF
-
-
SICSR register description
Reset source flags
AVDIE
Reserved, must be kept cleared
Reserved, must be kept cleared
Voltage detector interrupt enable
Voltage detector flag
LVD Reset flag
Watchdog Reset flag
R/W
6
This bit is set and cleared by software. It enables an interrupt to be generated
when the AVDF flag changes (toggles). The pending interrupt information is
automatically cleared when software enters the AVD interrupt routine
0: AVD interrupt disabled
1: AVD interrupt enabled
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an
interrupt request is generated when the AVDF bit changes value. Refer to
Figure 17
details.
0: V
1: V
This bit indicates that the last reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag
description for more details. When the LVD is disabled by option byte, the LVDRF
bit value is undefined.
This bit indicates that the last reset was generated by the Watchdog peripheral. It is
set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD
reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF information, the flag description is given in
External RESET pin
DD
DD
Reset sources
over V
under V
Watchdog
AVDF
and to
LVD
RO
5
IT+(AVD)
IT-(AVD)
Section 6.5.2: AVD (auxiliary voltage detector)
threshold
LVDRF
threshold
R/W
4
Function
3
Supply, reset and clock management
Reserved
LVDRF
2
-
0
0
1
Reset value: 000x 000x (00h)
1
for additional
WDGRF
Table
X
0
1
WDGRF
R/W
0
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13.