ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 44

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

Interrupts
Note:
7.3
Note:
7.4
44/193
peripheral control register. The general sequence for clearing an interrupt is based on an
access to the status register followed by a read or write to an associated register.
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be
serviced) is therefore lost if the clear sequence is executed.
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column Exit from Halt in
present while exiting Halt mode, the first one serviced can only be an interrupt with Exit from
Halt mode capability and it is selected through the same decision process shown in
Figure
If an interrupt, that is not able to exit from Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced after the first one serviced.
Concurrent and nested management
Figure 20
concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode
in
as follows: MAIN, IT4, IT3, IT2, IT1, IT0. Software priority is given for each interrupt.
Figure 20. Concurrent interrupt management
Figure
Warning:
19.
21. The interrupt hardware priority is given in order from the lowest to the highest
and
Figure 21
11/10
Main
RIM
A stack overflow may occur without notifying the software of
the failure.
IT2
Table 25: Interrupt
show two different interrupt management modes. The first is called
IT1
TRAP
IT1
mapping). When several pending interrupts are
IT0
IT3
IT4
10
Software
priority
level
Main
3
3
3
3
3
3
3/0
I1
1 1
1 1
1 1
1 1
1 1
1 1
ST72324Bxx
I0