ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 96

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

On-chip peripherals
Table 52.
10.4
10.4.1
10.4.2
Note:
96/193
Timer A: 36
Timer B: 46
Timer A: 37
Timer B: 47
Timer A: 3E
Timer B: 4E
Timer A: 3F
Timer B: 4F
Timer A: 38
Timer B: 48
Timer A: 39
Timer B: 49
Timer A: 3A
Timer B: 4A
Timer A: 3B
Timer B: 4B
Timer A: 3C
Timer B: 4C
Timer A: 3D
Timer B: 4D
Address
(Hex.)
16-bit timer register map and reset values (continued)
Serial peripheral interface (SPI)
Introduction
The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves.
However, the SPI interface can not be a master in a multi-master system.
Main features
●
●
●
●
●
●
●
●
●
In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
OC1HR
Reset value
OC1LR
Reset value
OC2HR
Reset value
OC2LR
Reset value
CHR
Reset value
CLR
Reset value
ACHR
Reset value
ACLR
Reset value
IC2HR
Reset value
IC2LR
Reset value
Register
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
6 master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master mode fault and Overrun flags
CPU
label
/2 max. slave mode frequency (see note)
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
7
1
0
1
0
1
1
1
1
x
x
6
0
0
0
0
1
1
1
1
x
x
CPU
/4 max.)
5
0
0
0
0
1
1
1
1
x
x
4
0
0
0
0
1
1
1
1
x
x
3
0
0
0
0
1
1
1
1
x
x
2
0
0
0
0
1
1
1
1
x
x
1
0
0
0
0
1
0
1
0
x
x
ST72324Bxx
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
0
0
0
0
0
1
0
1
0
x
x