ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 111

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

ST72324Bxx
10.5.4
Functional description
The block diagram of the serial control interface is shown in
dedicated registers:
●
●
●
●
●
Refer to the register descriptions in
Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame of ‘1’s followed by the start bit of the next
frame which contains data.
A Break character is interpreted on receiving ‘0’s for some multiple of the frame period. At
the end of the last break frame the transmitter inserts an extra ‘1’ bit to acknowledge the
start bit.
Transmission and reception are driven by their own baud rate generator.
Figure 58. Word length programming
2 control registers (SCICR1 and SCICR2)
a status register (SCISR)
a baud rate register (SCIBRR)
an extended prescaler receiver register (SCIERPR)
an extended prescaler transmitter register (SCIETPR)
Data frame
9-bit word length (M bit is set)
Start
bit
Data frame
8-bit word length (M bit is reset)
Start
bit
bit 0
bit 0
Figure
bit 1
bit 1
57).
bit 2
bit 2
bit 3
Section 10.5.7
bit 3
Idle frame
Break frame
Idle frame
Break frame
bit 4
bit 4
bit 5
bit 5
bit 6
for the definitions of each bit.
bit 6
Possible
bit 7 bit 8
Parity
bit 7
bit
Possible
Parity
bit
Figure
Stop
Bit
Stop
bit
Extra
Next data frame
Next
Start
Start
bit
bit
57. It contains six
’1’
Extra
Next data frame
Next
Start
Start
bit
bit
’1’
On-chip peripherals
Start
bit
Start
bit
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