ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 119

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

ST72324Bxx
Clock deviation causes
The causes which contribute to the total deviation are:
All the deviations of the system should be added and compared to the SCI clock tolerance:
Noise error causes
See also the description of Noise error in
Start bit
The Noise Flag (NF) is set during start bit reception if one of the following conditions occurs:
1.
2.
Therefore, a valid Start bit must satisfy both the above conditions to prevent the Noise Flag
from being set.
Data bits
The Noise Flag (NF) is set during normal data bit reception if the following condition occurs:
During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the
same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
Therefore, a valid Data bit must have samples 8, 9 and 10 at the same value to prevent the
Noise Flag from being set.
Figure 60. Bit sampling in Reception mode
–
–
–
–
A valid falling edge is not detected. A falling edge is considered to be valid if the three
consecutive samples before the falling edge occurs are detected as ‘1’ and, after the
falling edge occurs, during the sampling of the 16 samples, if one of the samples
numbered 3, 5 or 7 is detected as a ‘1’.
During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is
detected as a ‘1’.
Sample
clock
RDI line
D
the transmitter is transmitting at a different baud rate).
D
D
during the reception of one complete SCI message assuming that the deviation
has been compensated at the beginning of the message.
D
TRA
QUANT
REC
TCL
: Deviation due to the transmission line (generally due to the transceivers)
: Deviation due to transmitter error (local oscillator error of the transmitter or
: Deviation of the local oscillator of the receiver: This deviation can occur
: Error due to the baud rate quantization of the receiver.
1
2
D
3
TRA
4
+ D
7/16
QUANT
5
6
Receiver on page
+ D
7
sampled values
REC
One bit time
8
+ D
9
TCL
10
< 3.75%
11
113.
12
6/16
7/16
13
On-chip peripherals
14
15
16
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