ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 56

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

Power saving modes
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Figure 28. Halt timing overview
Figure 29. Halt mode flowchart
1. WDGHALT is an option bit. See
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
Table 25: Interrupt mapping
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
[MCCSR.OIE = 0]
Run
instruction
for more details.
Halt
N
Section 14.1 on page 179
WDGHALT
(MCCSR.OIE = 0)
Watchdog
Halt
Halt instruction
reset
1
Interrupt
Y
(1)
256 or 4096 CPU
(3)
Enable
cycle delay
interrupt
Reset
0
256 or 4096 CPU clock
Oscillator
Peripherals
CPU
Oscillator
Peripherals
CPU
Oscillator
Peripherals
CPU
I[1:0] bits
I[1:0] bits
I[1:0] bits
N
or
Fetch reset vector
or service interrupt
cycle
for more details.
Y
Reset
Watchdog
(2)
delay
Disable
vector
Fetch
XX
XX
on
off
on
on
on
on
10
off
off
off
(4)
(4)
Run
ST72324Bxx