ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 36

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

Supply, reset and clock management
Figure 15. RESET sequences
6.5
6.5.1
36/193
RESET pin
Watchdog
reset
External
RESET
source
V
V
IT+(LVD)
IT-(LVD)
System integrity management (SI)
The system integrity management block contains the LVD and auxiliary voltage detector
(AVD) functions. It is managed by the SICSR register.
LVD (low voltage detector)
The LVD function generates a static reset when the V
reference value. This means that it secures the power-up as well as the power-down
keeping the ST7 in reset.
The V
on in order to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).
The LVD reset circuitry generates a reset when V
The LVD function is illustrated in
The voltage threshold can be configured by option byte to be low, medium or high.
–
–
IT-
V
Run
DD
reference value for a voltage drop is lower than the V
V
V
IT+
IT-
when V
when V
Active phase
reset
LVD
DD
DD
is falling
is rising
t
h(RSTL)in
Figure
Run
15.
Watchdog underflow
phase
Active
External
reset
DD
is below:
DD
Internal reset (256 or 4096 T
Vector fetch
Run
supply voltage is below a V
IT+
Active
phase
Watchdog
t
w(RSTL)out
reset
reference value for power-
Run
ST72324Bxx
CPU
)
IT-