ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 42

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

Interrupts
7.2.1
42/193
Table 14.
Figure 18. Interrupt processing flowchart
Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:
●
●
Figure 19
Figure 19. Priority decision process flowchart
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
the highest software priority interrupt is serviced,
if several interrupts have the same software priority then the interrupt with the highest
hardware priority is serviced first.
describes this decision process.
Interrupt software priority
RESTORE PC, X, A, CC
Interrupt software priority levels
Reset
from stack
HIGHEST HARDWARE
PRIORITY SERVICED
Same
Y
Pending
I
instruction
Fetch next
nterrupt
I
nstruction
Execute
N
“IRET”
N
INTERRUPTS
SOFTWARE
PRIORITY
PENDING
HIGHEST SOFTWARE
PRIORITY SERVICED
Y
stays pending
The interrupt
Interrupt has the same or a
Level
Different
High
Low
lower software priority
load I1:0 from interrupt SW reg.
than current one
load PC from interrupt vector
Stack PC, X, A, CC
I1
1
0
0
1
TRAP
I1:0
N
ST72324Bxx
Y
I0
0
1
0
1