ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 38

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

Supply, reset and clock management
6.5.3
6.5.4
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The interrupt on the rising edge is used to inform the application that the V
is over.
If the voltage rise time t
selected by option byte), no AVD interrupt will be generated when V
If t
●
●
Figure 17. Using the AVD to monitor V
Low power modes
Table 10.
Interrupts
The AVD interrupt event generates an interrupt if the AVDIE bit is set and the interrupt mask
in the CC register is reset (RIM instruction).
Table 11.
M
rv
Mode
Wait
Interrupt event
Halt
is greater than 256 or 4096 cycles then:
If the AVD interrupt is enabled before the V
interrupts will be received: the first when the AVDIE bit is set, and the second when the
threshold is reached.
If the AVD interrupt is enabled after the V
AVD interrupt will occur.
AVDF bit
AVD Interrupt
Request
if AVDIE bit = 1
LVD RESET
AVD event
V
V
V
V
IT+(AVD)
IT+(LVD)
IT-(LVD)
IT-(AVD)
Effect of low power modes on SI
AVD interrupt control/wakeup capability
No effect on SI. AVD interrupt causes the device to exit from Wait mode.
The CRSR register is frozen.
V
DD
0
rv
is less than 256 or 4096 CPU cycles (depending on the reset delay
Event flag
AVDF
1
Interrupt process
V
Early warning interrupt
(power has dropped, MCU not
not yet in reset)
hyst
Enable control bit
Reset value
DD
AVDIE
IT+(AVD)
Description
IT+(AVD)
threshold is reached then only one
threshold is reached, then 2 AVD
Exit from Wait
t
1
rv
Yes
Voltage rise time
IT+(AVD)
Interrupt process
DD
0
is reached.
Exit from Halt
warning state
ST72324Bxx
No