MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 112

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2
The following table summarizes the effect on the various configuration bits - data direction (DDR), input
/ output level (I/O), reduced drive (RDR), pull enable (PE), pull select (PS) and interrupt enable (IE) for
the ports. The configuration bit PS is used for two purposes:
112
1
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
DDR
Applicable only on ports G, H, and J.
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Register Descriptions
IO
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
All bits of all registers in this module are completely synchronous to internal
clocks during a register read.
RDR
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
PE
X
X
X
X
X
X
X
X
0
1
1
0
0
1
1
Table 3-3. Pin Configuration Summary
PS
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
MC9S12NE64 Data Sheet, Rev. 1.1
IE
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
NOTE
NOTE
Output, reduced drive to 0
Output, reduced drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Output, full drive to 0
Output, full drive to 1
Output, full drive to 0
Output, full drive to 1
Function
Input
Input
Input
Input
Input
Input
Input
Pull Device
Pull Down
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Pull Up
Pull Up
Freescale Semiconductor
Falling edge
Falling edge
Falling edge
Falling edge
Rising edge
Rising edge
Rising edge
Rising edge
Interrupt
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled