MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 330

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 11 Ethernet Media Access Controller (EMACV1)
TXBYT — Transmit Frame Byte Counter
BSLOT — Backoff Slot Time Counter
RETX — Retransmission Counter
RANDOM — Backoff Random Number
11.4
The EMAC provides a 10/100 Mbps Ethernet media access control (MAC) function and is designed to
connect to a PHY device supporting MII. The EMAC is an 802.3 compliant Ethernet controller specifically
optimized for 8-/16-bit embedded processors. The main components of the EMAC are the receiver,
transmitter, MAC flow control, MII management, and receive and transmit Ethernet buffer interfaces.
11.4.1
In an Ethernet network, information is received or transmitted in the form of a frame. The frame format
used for Ethernet consists of preamble (PA), start frame delimiter (SFD), destination address (DA), source
address (SA), type/length field, data field, and frame check sequence (FCS). See
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This11-bit read-only field indicates the number of bytes of the current frame that have been read from
the transmit buffer by the EMAC transmitter. This register does not include transmitted pad data that
is added to frames if less than the minimum amount of data is transmitted nor the FCS data that is
appended to the end of transmit frames. While sending pause frames with the PAUSE command, this
register is ignored.
This 10-bit read-only field indicates the number of slot times (512 bit times) in progress during the
backoff delay. This counter clears at the end of backoff delay, which is set by the random algorithm.
The MISC[10] bit reads 0.
This 4-bit read-only field indicates the current retransmission count if retransmission takes place due
to collision. The MISC[10:4] bits read 0.
This10-bit read-only random number is generated for use by the backoff logic. The value returned
when reading this field is random if the transmitter is enabled. The MISC[10] bit reads 0.
Preamble
7 bytes
Functional Description
Ethernet Frame
Start Frame
Delimiter
1 bytes
Destination
Address
6 bytes
Table 11-9. Ethernet Frame Structure
Index
0-2
Table 11-8. Miscellaneous Fields
3
4
5
6
7
MC9S12NE64 Data Sheet, Rev. 1.1
Address
RANDOM
Reserved
Source
6 bytes
BSLOT
TXBYT
RETX
Field
None
Type/ Length
Retransmissions
2 bytes
Reserved
Slot time
Read 0s
Bytes
Unit
N/A
46 to 1500 bytes
Data
Table
Freescale Semiconductor
11-9.
Frame Check
Sequence
4 bytes