MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 212

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 7 Analog-to-Digital Converter (ATD10B8CV3)
7.3.2.1
Writes to this register will abort current conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
212
WRAP[2:0]
ATDD47H
ATDD47L
Reset
Register
Field
Name
2–0
W
R
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
multi-channel conversions. The coding is summarized in
ATD Control Register 0 (ATDCTL0)
0
0
7
10-BIT
10-BIT
8-BIT
8-BIT
WRAP2
W
= Unimplemented or Reserved
0
0
0
0
1
1
1
1
BIT 7 MSB
BIT 7
Bit 7
0
0
6
0
0
Figure 7-2. ATD Register Summary (Sheet 5 of 5)
Figure 7-3. ATD Control Register 0 (ATDCTL0)
Table 7-2. Multi-Channel Wrap Around Coding
WRAP1
0
0
1
1
0
0
1
1
= Unimplemented or Reserved
Table 7-1. ATDCTL0 Field Descriptions
BIT 6
BIT 6
6
0
0
MC9S12NE64 Data Sheet, Rev. 1.1
0
0
5
WRAP0
0
1
0
1
0
1
0
1
BIT 5
BIT 5
5
0
0
Multiple Channel Conversions (MULT = 1)
0
0
4
Wrap Around to AN0 after Converting
Description
BIT 4
BIT 4
4
0
0
Table
0
0
3
Reserved
7-2.
BIT 3
BIT 3
AN1
AN2
AN3
AN4
AN5
AN6
AN7
3
0
0
WRAP2
1
2
BIT 2
BIT 2
2
0
0
WRAP1
Freescale Semiconductor
BIT 9 MSB
1
1
BIT 1
BIT 1
1
0
WRAP0
BIT 8
BIT 0
BIT 0
Bit 0
1
0
0