MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 502

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Appendix A Electrical Characteristics
A.3
There are four groups of functional pins.
A.3.1
These I/O pins have a nominal level of 3.3 V. This group of pins is comprised of all port I/O pins,
the analog inputs, BKGD pin and the RESET inputs. The internal structure of these pins are
identical, however some of the functionality may be disabled.
A.3.2
This group of pins is comprised of the V
PHY_RXP, and R
502
• PHY_VDDTX, PHY_VSSTX are power supply pins for EPHY transmitter
• V
diodes for ESD protection.
DDA
Pins
3.3 V I/O Pins
Analog Reference, Special Function Analog
, V
In the following context:
• V
• V
• I
• V
• V
• I
• I
• V
• V
• I
DDX1
otherwise noted
V
PHY_VDDRX, and PHY_VDDA
and PHY_VSSA
PHY_VDDTX, PHY_VDDRX, and PHY_VDDA
PHY_VDDA
PHY_TXP and PHY_TXN pins
PHY_TXP or PHY_TXN pins
BIAS
DD3
DD
DDPHY
DDTX
DD3
SS3
DDR
DD
SS
DDPHY
DDTX
, V
is used for the sum of the currents flowing into V
is used for V
denotes the sum of the currents flowing into the V
is used for V
is used for either V
pins.
, and V
is used for either V
is used for twisted pair differential current flowing into the
DDX2
is used for twisted pair differential voltage present on the
is used for the sum of currents flowing into
is used for PHY_VDDTX, PHY_VDDRX, and
as well as V
DDX1
SS1
MC9S12NE64 Data Sheet, Rev. 1.1
DD1
/V
, V
DDX2
, V
SS2
RH
SSA
DD2
SSA
DDA
, V
, V
pins
NOTE
, V
, V
, V
RL
SSPL
, V
SSR
, PHY_TXN, PHY_TXP, PHY_RXN,
SSX1
DDPLL
DDR
, PHY_VSSTX, PHY_VSSRX,
, and V
, V
, and V
, PHY_VDDTX,
SSX2
SSX1
DDX1
are connected by anti-parallel
/V
SSX2
/V
DDX2
DD1
unless
DDA
, V
,
Freescale Semiconductor
DD2