MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 407

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.3.2.8
Read: Anytime (provided this register is in the map).
Write: Each bit has specific write conditions. Please refer to the descriptions of each bit on the following
pages.
Port E serves as general-purpose I/O or as system and bus control signals. The PEAR register is used to
choose between the general-purpose I/O function and the alternate control functions. When an alternate
control function is selected, the associated DDRE bits are overridden.
The reset condition of this register depends on the mode of operation because bus control signals are
needed immediately after reset in some modes. In normal single-chip mode, no external bus control signals
are needed so all of port E is configured for general-purpose I/O. In normal expanded modes, only the E
clock is configured for its alternate bus control function and the other bits of port E are configured for
general-purpose I/O. As the reset vector is located in external memory, the E clock is required for this
access. R/W is only needed by the system when there are external writable resources. If the normal
expanded system needs any other bus control signals, PEAR would need to be written before any access
that needed the additional signals. In special test and emulation modes, IPIPE1, IPIPE0, E, LSTRB, and
R/W are configured out of reset as bus control signals.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
Freescale Semiconductor
Normal Expanded Wide
Emulation Expanded
Emulation Expanded
Special Single Chip
Normal Single Chip
Normal Expanded
Special Test
Peripheral
Port E Assignment Register (PEAR)
Narrow
Narrow
Reset
Wide
W
R
NOACCE
0
0
0
1
1
0
0
0
7
Figure 15-12. Port E Assignment Register (PEAR)
= Unimplemented or Reserved
0
0
0
0
0
0
0
0
0
6
MC9S12NE64 Data Sheet, Rev. 1.1
PIPOE
0
1
0
1
1
0
0
0
5
NECLK
4
0
0
0
0
0
1
0
0
LSTRE
0
1
0
1
1
0
0
0
3
RDWE
Memory Map and Register Definition
0
1
0
1
1
0
0
0
2
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
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