MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 249

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.5
8.4.5.1
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
8.4.5.2
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data
register is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
Freescale Semiconductor
FROM TXD PIN
OR TRANSMITTER
SCRXD
LOOPS
Receiver
RSRC
RDRF/OR INTERRUPT REQUEST
Receiver Character Length
Character Reception
TDRE flag is set and immediately before writing the next byte to the SCI
data register.
If the TE bit is clear and the transmission is complete, the SCI is not the
master of the TXD pin
IDLE INTERRUPT REQUEST
CONTROL
LOOP
SBR12–SBR0
CLOCK
BUS
Figure 8-14. SCI Receiver Block Diagram
WAKE
DIVIDER
RAF
BAUD
ILT
RE
PE
PT
M
MC9S12NE64 Data Sheet, Rev. 1.1
RECOVERY
DATA
CHECKING
WAKEUP
PARITY
LOGIC
INTERNAL BUS
IDLE
ILIE
RIE
H
11-BIT RECEIVE SHIFT REGISTER
8
7
SCI DATA REGISTER
RDRF
OR
6
5
R8
4
FE
NF
PE
3
2
Functional Description
1
0
L
RWU
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