MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 215

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.3.2.4
This register controls the conversion sequence length, FIFO for results registers and behavior in freeze
mode. Writes to this register will abort current conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
S8C, S4C,
S2C, S1C
Reset
ASCIE
ASCIF
Field
Field
6–3
1
0
W
R
Conversion Sequence Length — These bits control the number of conversions per sequence.
all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12
Family.
ATD Control Register 3 (ATDCTL3)
0
0
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Interrupt will be requested whenever ASCIF = 1 is set.
ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see
Section 7.3.2.7, “ATD Status Register 0
0 No ATD interrupt occurred
1 ATD sequence complete interrupt pending
7
= Unimplemented or Reserved
S8C
0
6
ETRIGLE
Table 7-5. ATDCTL2 Field Descriptions (continued)
Figure 7-6. ATD Control Register 3 (ATDCTL3)
0
0
1
1
Table 7-6. External Trigger Configurations
Table 7-7. ATDCTL3 Field Descriptions
S4C
MC9S12NE64 Data Sheet, Rev. 1.1
0
5
ETRIGP
0
1
0
1
(ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.
S2C
0
4
Description
Description
External Trigger Sensitivity
S1C
0
3
Falling edge
Rising edge
High level
Low level
FIFO
0
2
Memory Map and Register Definition
FRZ1
0
1
Table 7-8
FRZ0
0
0
shows
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