MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 519

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

The following procedure can be used to calculate the resistance and capacitance values using typical values
for K
The grey boxes show the calculation for f
for f
The VCO Gain at the desired VCO frequency is approximated by:
The phase detector relationship is given by:
i
The loop bandwidth f
typical values are 50. ζ = 0.9 ensures a good transient response.
Freescale Semiconductor
ch
is the current in tracking mode.
OSC
1
, f
1
= 4 MHz and a 25 MHz bus clock.
and i
ch
from Table A-13.
f
osc
K
V
C
f
should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
C
=
K
<
refdv+1
K
Φ
------------------------------------------
π
1
Figure 18-22. Basic PLL Functional Diagram
⋅
=
1
⋅
⎛
⎝
2 ζ f
e
ζ
–
(
---------------------- -
⋅ ⋅
+
f
K
i
1
ch
MC9S12NE64 Data Sheet, Rev. 1.1
1
f
–
ref
⋅
V
1
f
VCO
1V
vco
⋅
ref
DDPLL
+
K
=
)
V
ζ
= 50 MHz and f
2
–
⎞
⎠
100
∆
f
----- -
10
cmp
1
C
C
⋅
p
→
Loop Divider
e
s
Detector
(
----------------------
= 316.7Hz/Ω
Phase
60 50
synr+1
f
–
f
K
C
C
100
Φ
ref
–
1
<
R
< 25kHz
= 1 MHz. E.g., these frequencies are used
Reset, Oscillator, and PLL Electrical Characteristics
------------ - ζ
4 10
= -90.48MHz/V
f
)
ref
⋅
;
(
XFC Pin
=
0.9
1
2
VCO
)
K
V
f
vco
519