MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 298

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 10 Inter-Integrated Circuit (IICV2)
10.4.1.2
The first byte of data transfer immediately after the START signal is the slave address transmitted by the
master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
Only the slave with a calling address that matches the one transmitted by the master will respond by
sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see
No two slaves in the system may have the same address. If the IIC bus is master, it must not transmit an
address that is equal to its own slave address. The IIC bus cannot be master and slave at the same
time.However, if arbitration is lost during an address cycle the IIC bus will revert to slave mode and operate
correctly even if it is being addressed by another master.
10.4.1.3
As soon as successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a
direction specified by the R/W bit sent by the calling master
All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address
information for the slave device.
Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while
SCL is high as shown in
transferred first. Each data byte has to be followed by an acknowledge bit, which is signalled from the
receiving device by pulling the SDA low at the ninth clock. So one complete data byte transfer needs nine
clock pulses.
If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The
master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to
commence a new calling.
298
SCL
SDA
1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
Slave Address Transmission
Data Transfer
START Condition
Figure
10-9. There is one clock pulse on SCL for each data bit, the MSB being
Figure 10-10. Start and Stop Conditions
MC9S12NE64 Data Sheet, Rev. 1.1
STOP Condition
Freescale Semiconductor
Figure
10-9).