MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 368

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 12 Ethernet Physical Transceiver (EPHYV2)
12.4.1
Upon reset, the EPHYEN bit, in the Ethernet physical transceiver control register 0 (EPHYCTL0), is
cleared and EPHY is in its lowest power consumption state. All analog circuits are powered down. The
twisted-pair transmitter and receiver pins (PHY_TXP, PHY_TXN, PHY_RXP, and PHY_RXN) are
high-impedance. The MII management interface is not accessible. All MII registers are initialized to their
reset state. The ANDIS, DIS100, and DIS10 bits, in the EPHYCTL0 register, have no effect until the
EPHYEN bit is set.
The EPHYEN bit can be set or cleared by a register write at any time. Prior to enabling the EPHY, setting
EPHYEN to 1, the MII PHY address PHYADD[4:0] must be set in the Ethernet physical transceiver
control register 1 (EPHYCTL1), and the ANDIS, DIS100, DIS10 bits, in the EPHYCTL0 register, must
be configured for the desired start-up operation. Whenever the EPHYEN bit transitions from 0 to 1, MDIO
communications must be delayed until the completion of a start-up delay period (t
Figure
368
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•
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12-19).
10BASE-T
100BASE-TX
Low-power
Power Down/Initialization
MC9S12NE64 Data Sheet, Rev. 1.1
Start-up
Freescale Semiconductor
, see