MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 208

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 7 Analog-to-Digital Converter (ATD10B8CV3)
7.3
This section provides a detailed description of all registers accessible in the ATD.
7.3.1
Figure 7-2
7.3.2
This section describes in address order all the ATD registers and their individual bits.
208
Unimplemente
ATDTEST0
ATDTEST1
ATDSTAT0
ATDCTL0
ATDCTL1
ATDCTL2
ATDCTL3
ATDCTL4
ATDCTL5
Register
Name
d
Memory Map and Register Definition
gives an overview of all ATD registers.
Module Memory Map
Register Descriptions
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
ETRIGSEL
SRES8
ADPU
Bit 7
DJM
SCF
U
U
0
0
Figure 7-2. ATD Register Summary (Sheet 1 of 5)
= Unimplemented or Reserved
DSGN
SMP1
AFFC
S8C
U
U
6
0
0
0
MC9S12NE64 Data Sheet, Rev. 1.1
ETORF
SCAN
SMP0
AWAI
S4C
U
5
0
0
0
NOTE
ETRIGLE
FIFOR
PRS4
MULT
S2C
U
4
0
0
0
ETRIGP
PRS3
S1C
U
3
0
0
0
0
0
ETRIGCH2 ETRIGCH1 ETRIGCH0
ETRIGE
WRAP2
PRS2
FIFO
CC2
CC
U
2
0
Freescale Semiconductor
WRAP1
ASCIE
PRS1
FRZ1
CC1
CB
U
1
0
WRAP0
ASCIF
PRS0
FRZ0
Bit 0
CC0
CA
SC
U