MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 62

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 1 MC9S12NE64 Device Overview
1.5.3
This mode is entered by executing the CPU WAI instruction. In this mode, the CPU will not execute
instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.
For further power consumption, the peripherals can individually turn off their local clocks.
1.5.4
Although this is not a low-power mode, unused peripheral modules must not be enabled in order to save
power.
1.6
See the exception processing section of the CPU12 reference manual for information on resets and
interrupts. System resets can be generated through external control of the RESET pin, through the clock
and reset generator module (CRG), or through the low-voltage reset (LVR) generator of the voltage
regulator module. See the CRG and VREG_PHY block description sections for detailed information on
reset generation.
1.6.1
Table 1-7
62
Vector
through
No.
11
12
13
14
15
0
1
2
3
4
5
6
7
8
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFE8 to $FFEF
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
Resets and Interrupts
lists interrupt sources and vectors in default order of priority.
Address
Wait
Run
Vectors
Vector
Vclkmon
Vtimch4
Vtimch5
Vtimch6
Vtimch7
Vector
Name
Vreset
Vcop
Vtrap
Vxirq
Vswi
Virq
Vrti
Table 1-7. Interrupt Vector Locations
low voltage reset (see CRG flags
External reset, power on reset or
Unimplemented instruction trap
MC9S12NE64 Data Sheet, Rev 1.0
register to determine reset
Standard timer channel 4
Standard timer channel 5
Standard timer channel 6
Standard timer channel 7
Clock monitor fail reset
Interrupt Source
Real-time interrupt
COP failure reset
source)
XIRQ
SWI
IRQ
Reserved
Mask
CCR
None
None
None
None
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
COPCTL (CME,
INTCR (IRQEN)
COP rate select
CRGINT (RTIE)
Local Enable
T0IE (T0C4I)
T0IE (T0C5I)
T0IE (T0C6I)
T0IE (T0C7I)
FCME)
None
None
None
None
Freescale Semiconductor
HPRIO Value
to Elevate
$F2
$F0
$E6
$E4
$E2
$E0
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