MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 414

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 15 Multiplexed External Bus Interface (MEBIV3)
15.3.2.13 Reserved Register
This register location is not used (reserved). All bits in this register return logic 0s when read. Writes to
this register have no effect.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
15.3.2.14 IRQ Control Register (IRQCR)
Read: See individual bit descriptions below
Write: See individual bit descriptions below
414
IRQEN
Field
IRQE
7
6
Reset
Reset
W
W
R
R
IRQ Select Edge Sensitive Only
Special modes: read or write anytime
Normal and Emulation modes: read anytime, write once
0 IRQ configured for low level recognition.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime
External IRQ Enable
Normal, emulation, and special modes: read or write anytime
0 External IRQ pin is disconnected from interrupt logic.
1 External IRQ pin is connected to interrupt logic.
Note: When IRQEN = 0, the edge detect latch is disabled.
IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
IRQE
7
0
0
7
0
= Unimplemented or Reserved
= Unimplemented or Reserved
IRQEN
6
0
0
6
1
Figure 15-18. IRQ Control Register (IRQCR)
Table 15-12. IRQCR Field Descriptions
Figure 15-17. Reserved Register
MC9S12NE64 Data Sheet, Rev. 1.1
5
0
0
5
0
0
0
0
0
0
Description
4
4
0
0
0
0
3
3
0
0
0
0
2
2
Freescale Semiconductor
0
0
0
0
1
1
0
0
0
0
0
0