MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 132

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2.6.3
Read:Anytime.
Write:Anytime.
DDRL[6:0] — Data Direction Port L
This register configures each port L pin as either input or output. If EPHY port status LEDs are enabled,
pins PL[4:0] are forced to be outputs and this register has no effect on their directions. Refer to the EPHY
block description chapter for more information.
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTL
or PTIL registers, when changing the DDRL register.
3.3.2.6.4
Read:Anytime.
Write:Anytime.
This register configures the drive strength of each port L output pin as either full or reduced. If the port is
used as input this bit is ignored.
RDRL[6:0] — Reduced Drive Port L
132
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
Module Base + $2A
Module Base + $2B
Reset:
Reset:
Read:
Read:
Write:
Write:
Data Direction Register (DDRL)
Reduced Drive Register (RDRL)
Bit 7
Bit 7
—
—
0
0
= Reserved or unimplemented
= Reserved or unimplemented
DDRL6
RDRL6
Figure 3-42. Port L Reduced Drive Register (RDRL)
Figure 3-41. Port L Data Direction Register (DDRL)
6
0
6
0
MC9S12NE64 Data Sheet, Rev. 1.1
DDRL5
RDRL5
5
0
5
0
DDRL4
RDRL4
4
0
4
0
DDRL3
RDRL3
3
0
3
0
DDRL2
RDRL2
2
0
2
0
DDRL1
RDRL1
1
0
1
0
Freescale Semiconductor
DDRL0
RDRL0
Bit 0
Bit 0
0
0