MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 374

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 12 Ethernet Physical Transceiver (EPHYV2)
12.4.4.1 Sublayers
12.4.4.1.1
The PCS sublayer is the MII interface that provides a uniform interface to the reconciliation sublayer.
The services provided by the PCS include:
Serial to Parallel and Symbol Alignment: This block looks for the occurrence of the JK symbol to align
the serial bit stream and convert it to a parallel format.
Carrier Sense: In full-duplex mode, carrier sense is only asserted while the receive channel is active. The
carrier sense examines the received data bit stream looking for the SSD, the JK symbol pair. In the idle
state, IDLE symbols (all logic ones) will be received. If the first 5-bit symbols received after an idle stream
forms the J symbol (11000) it asserts the CRS signal. At this point the second symbol is checked to confirm
the K symbol (10001). If successful, the following aligned data (symbols) are presented to the 4B/5B
decoder. If the JK pair is not confirmed, the false carrier detect is asserted and the idle state is re-entered.
Carrier sense is de-asserted when the ESD (end-of-stream) delimiter, the TR symbol pair, is found, or when
an idle state is detected.
In half-duplex, CRS is also asserted on transmit.
Parallel to Serial: This block takes parallel data and converts it to serial format.
374
TX
RX
•
•
•
•
MII
Encoding/decoding of MII data nibbles to/from 5-bit code-groups (4B/5B)
Carrier sense and collision indications
Serialization/deserialization of code-groups for transmission/reception on the PMA
Mapping of transmit, receive, carrier sense, and collision detection between the MII and the
underlying PMA
PCS Sublayer
DECODER
ENCODER
4B5B
PCS
4B5B
AND SYMBOL
ALIGNMENT
SERIAL TO
PARALLEL
CARRIER
PARALLEL
SENSE
SERIAL
TO
Figure 12-22. 100BASE-TX Block Diagram
MC9S12NE64 Data Sheet, Rev. 1.1
PMA
PMA
SCRAMBLER
DESCRAMBLER
ENCODER
MLT3
DECODER
PMD
MLT3
LOOPBACK
(bit 0.14)
DIGITAL
CONTROL
LOOPBACK
SLOPE
EQUALIZER
RECOVERY
(bit 18.4)
ANALOG
TIMING
AND
Freescale Semiconductor
BASELINE
WANDER
MONITOR
DRIVER
LINK
LINE