MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 163

• Manufacturer Part Number: MC912DG128ACPV
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128ACPV

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

12.6 Limp-Home and Fast STOP Recovery modes
12.6.1 Clock Loss during Normal Operation
MC68HC912DT128A — Rev 4.0
MOTOROLA
If the crystal frequency is not available due to a crystal failure or a long
crystal start-up time, the MCU system clock can be supplied by the VCO
at its minimum operating frequency, f
called Limp-Home Mode and is only available when the VDDPLL supply
voltage is at VDD level (i.e. power supply for the PLL module is present).
Upon power-up, the ability of the system to start in Limp-Home Mode is
restricted to normal MCU modes only.
The Clock Monitor circuit (see section Clock Monitor) can detect the loss
of EXTALi, the external clock input signal, regardless of whether this
signal is used as the source for MCU clocks or as the PLL reference
clock. The clock monitor control bits, CME and FCME, are used to
enable or disable external clock detection.
A missing external clock may occur in the three following instances:
The ‘no limp-home mode’ bit, NOLHM, determines how the MCU
responds to an external clock loss in this case.
With limp home mode disabled (NOLHM bit set) and the clock monitor
enabled (CME or FCME bits set), on a loss of clock the MCU is reset via
the clock monitor reset vector. A latch in the PLL control section prevents
the chip exiting reset in Limp Home Mode (this is required as the NOLHM
bit gets cleared bu reset). Only external clock activity can bring the MCU
out from this reset state. Once reset has been exited, the latch is cleared
and another session, with or without Limp Home Mode enabled, can
take place. This is the same behavior as standard M68HC12 circuits
without PLL or operation with VDDPLL at VSS level.
With limp home mode enabled (NOLHM bit cleared) and the clock
monitor enabled (CME or FCME bits set), on a loss of clock, the PLL
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Freescale Semiconductor, Inc.
For More Information On This Product,
During normal clock operation.
At Power-On Reset.
In the STOP exit sequence
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Clock Functions
Limp-Home and Fast STOP Recovery modes
VCOMIN
. This mode of operation is
Clock Functions
Technical Data
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