MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 314

no-image

MC912DG128ACPV

Manufacturer Part Number
MC912DG128ACPV
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128ACPV

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC912DG128ACPV
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC912DG128ACPV
Manufacturer:
FREE
Quantity:
20 000
Part Number:
MC912DG128ACPV 5K91D
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC912DG128ACPVE
Manufacturer:
MICREL
Quantity:
9 982
Part Number:
MC912DG128ACPVE
Manufacturer:
FREESCALE
Quantity:
1 200
Part Number:
MC912DG128ACPVE
Manufacturer:
FREESCALE
Quantity:
1 970
Part Number:
MC912DG128ACPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC912DG128ACPVE
Manufacturer:
FREESCALE
Quantity:
1 970
Part Number:
MC912DG128ACPVER
Manufacturer:
STM
Quantity:
1 244
Part Number:
MC912DG128ACPVER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Inter IC Bus
Technical Data
314
IBSR — IIC Bus Status Register
RESET:
Bit 7
TCF
1
IAAS
RSTA — Repeat Start
IBSWAI — IIC Stop in WAIT mode
TCF — Data transferring bit
IAAS — Addressed as a slave bit
IBB — IIC Bus busy bit
6
0
Writing a 1 to this bit will generate a repeated START condition on the
bus, provided it is the current bus master. This bit will always be read
as a low. Attempting a repeated start at the wrong time, if the bus is
owned by another master, will result in loss of arbitration.
This status register is read-only with exception of bit 1 (IBIF) and bit 4
(IBAL), which are software clearable
While one byte of data is being transferred, this bit is cleared. It is set
by the falling edge of the 9th clock of a byte transfer.
When its own specific address (IIC Bus Address Register) is matched
with the calling address, this bit is set. The CPU is interrupted
provided the IBIE is set. Then the CPU needs to check the SRW bit
and set its Tx/Rx mode accordingly. Writing to the IIC Bus Control
Register clears this bit.
This bit indicates the status of the bus. When a START signal is
detected, the IBB is set. If a STOP signal is detected, it is cleared.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Generate repeat start cycle
0 = IIC module operates normally
1 = Halt clock generation of IIC module in WAIT mode
0 = Transfer in progress
1 = Transfer complete
0 = Not addressed
1 = Addressed as a slave
0 = Bus is idle
1 = Bus is busy
IBB
5
0
Go to: www.freescale.com
IBAL
Inter IC Bus
4
0
3
0
0
SRW
2
0
MC68HC912DT128A — Rev 4.0
IBIF
1
0
RXAK
Bit 0
0
MOTOROLA
$00E3

Related parts for MC912DG128ACPV