MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 38

• Manufacturer Part Number: MC912DG128ACPV
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128ACPV

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Central Processing Unit
2.5 Addressing Modes
Technical Data
38
(auto post-increment)
(auto pre-decrement)
(auto pre-increment)
(accumulator offset)
Addressing Mode
Indexed-Indirect
Indexed-Indirect
(D accumulator
(16-bit offset)
(16-bit offset)
(5-bit offset)
(9-bit offset)
decrement)
(auto post-
Immediate
Extended
Inherent
Relative
Indexed
Indexed
Indexed
Indexed
Indexed
Indexed
Indexed
Indexed
offset)
Direct
(no externally supplied
INST [oprx16,xysp]
Table 2-1. M68HC12 Addressing Mode Summary
INST oprx16,xysp
INST oprx3,+xys
INST oprx3,xys+
INST oprx5,xysp
INST oprx3,–xys
INST oprx3,xys–
INST oprx9,xysp
Source Format
INST abd,xysp
INST [D,xysp]
Addressing modes determine how the CPU accesses memory locations
to be operated upon. The CPU12 includes all of the addressing modes
of the M68HC11 CPU as well as several new forms of indexed
addressing.
INST #opr16i
INST opr16a
INST #opr8i
INST opr8a
INST rel16
operands)
INST rel8
Freescale Semiconductor, Inc.
INST
or
or
For More Information On This Product,
Table 2-1
Go to: www.freescale.com
Central Processing Unit
Abbreviation
[D,IDX]
[IDX2]
IDX1
IDX2
IMM
EXT
REL
INH
DIR
IDX
IDX
IDX
IDX
IDX
IDX
is a summary of the available addressing modes.
Operand is the lower 8-bits of an address in the
An 8-bit or 16-bit relative offset from the current
5-bit signed constant offset from x, y, sp, or pc
9-bit signed constant offset from x, y, sp, or pc
(lower 8-bits of offset in one extension byte)
Operand is included in instruction stream
Auto post-decrement x, y, or sp by 1 ~ 8
16-bit constant offset from x, y, sp, or pc
16-bit constant offset from x, y, sp, or pc
Auto post-increment x, y, or sp by 1 ~ 8
Auto pre-decrement x, y, or sp by 1 ~ 8
Indexed with 8-bit (A or B) or 16-bit (D)
Operands (if any) are in CPU registers
Auto pre-increment x, y, or sp by 1 ~ 8
accumulator offset from x, y, sp, or pc
(16-bit offset in two extension bytes)
(16-bit offset in two extension bytes)
8- or 16-bit size implied by context
x, y, sp, or pc plus the value in D
Pointer to operand is found at...
Pointer to operand is found at...
pc is supplied in the instruction
Operand is a 16-bit address
range $0000 – $00FF
MC68HC912DT128A — Rev 4.0
Description
MOTOROLA