MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 257

• Manufacturer Part Number: MC912DG128ACPV
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128ACPV

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TMSK2 — Timer Interrupt Mask 2
MC68HC912DT128A — Rev 4.0
MOTOROLA
RESET:
Bit 7
TOI
0
6
0
0
Read or write anytime.
TOI — Timer Overflow Interrupt Enable
PUPT — Timer Port Pull-Up Resistor Enable
RDPT — Timer Port Drive Reduction
TCRE — Timer Counter Reset Enable
PR2, PR1, PR0 — Timer Prescaler Select
This enable bit controls pull-up resistors on the timer port pins when
the pins are configured as inputs.
This bit reduces the effective output driver size which can reduce
power supply current and generated noise depending upon pin
loading.
This bit allows the timer counter to be reset by a successful output
compare 7 event. This mode of operation is similar to an up-counting
modulus counter.
If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously.
If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT is
reset from $FFFF to $0000.
These three bits specify the number of ÷2 stages that are to be
inserted between the module clock and the main timer counter.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Interrupt inhibited
1 = Hardware interrupt requested when TOF flag set
0 = Disable pull-up resistor function
1 = Enable pull-up resistor function
0 = Normal output drive capability
1 = Enable output drive reduction function
0 = Counter reset inhibited and counter free runs
1 = Counter reset by a successful output compare 7
PUPT
5
0
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Enhanced Capture Timer
RDPT
4
0
TCRE
3
0
PR2
2
0
PR1
1
0
Timer Register Descriptions
Enhanced Capture Timer
Bit 0
PR0
0
Technical Data
$008D
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