MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 53

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MC912DG128ACPV

Manufacturer Part Number
MC912DG128ACPV
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128ACPV

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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3.4.11 Instruction Queue Tracking Signals (IPIPE1 and IPIPE0)
3.4.12 Data Bus Enable (DBE)
3.4.13 Inverted E clock (ECLK)
3.4.14 Calibration reference (CAL)
MC68HC912DT128A — Rev 4.0
MOTOROLA
IPIPE1 (PE6) and IPIPE0 (PE5) signals are used to track the state of the
internal instruction queue. Data movement and execution state
information is time-multiplexed on the two signals. Refer to
Support.
The DBE pin (PE7) is an active low signal that will be asserted low during
E-clock high time. DBE provides separation between output of a
multiplexed address and the input of data. When an external address is
stretched, DBE is asserted during what would be the last quarter cycle
of the last E-clock cycle of stretch. In expanded modes this pin is used
to enable the drive control of external buses during external reads. Use
of the DBE is controlled by the NDBE bit in the PEAR register. DBE is
enabled out of reset in expanded modes.
The ECLK pin (PE7) can be used to latch the address for de-
multiplexing. It has the same behavior as the ECLK, except is inverted.
In expanded modes this pin is used to enable the drive control of external
buses during external reads. Use of the ECLK is controlled by the NDBE
and DBENE bits in the PEAR register.
The CAL pin (PE7) is the output of the Slow Mode programmable clock
divider, SLWCLK, and is used as a calibration reference. The SLWCLK
frequency is equal to the crystal frequency out of reset and always has
a 50% duty. If the DBE function is enabled it will override the enabled
CAL output. The CAL pin output is disabled by clearing CALE bit in the
PEAR register.
Freescale Semiconductor, Inc.
For More Information On This Product,
Pinout and Signal Descriptions
Go to: www.freescale.com
Pinout and Signal Descriptions
Signal Descriptions
Development
Technical Data
53

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