MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 60

• Manufacturer Part Number: MC912DG128ACPV
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128ACPV

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pinout and Signal Descriptions
3.5.7 Port CAN2
(MC68HC912DT128A only)
3.5.8 Port CAN1
Technical Data
60
for general purpose I/O. Port K bit 3 is used as a general purpose I/O pin
only. The port data register is not in the address map during expanded
and peripheral mode operation with EMK set. When it is in the map, port
K can be read or written at anytime.
Register DDRK determines whether each port K pin is an input or output.
DDRK is not in the address map during expanded and peripheral mode
operation with EMK set. Setting a bit in DDRK makes the corresponding
bit in port K an output; clearing a bit in DDRK makes the corresponding
bit in port K an input. The default reset state of DDRK is all zeroes.
When the PUPK bit in the PUCR register is set, all port K input pins are
pulled-up internally by an active pull-up device. PUCR is not in the
address map in peripheral mode.
Setting the RDPK bit in register RDRIV causes all port K outputs to have
reduced drive level. RDRIV can be written once after reset. RDRIV is not
in the address map in peripheral mode. Refer to
Input/Output.
The MSCAN2 uses two external pins, one input (RxCAN2) and one
output (TxCAN2). The TxCAN2 output pin represents the logic level on
the CAN: ‘0’ is for a dominant state, and ‘1’ is for a recessive state.
RxCAN2 is on bit 0 of Port CAN2, TxCAN2 is on bit 1. If the MSCAN2 is
not used, TxCAN2 should be left unconnected and, due to an internal
pull-up, the RxCAN2 pin should not be tied to VSS.
The MSCAN1 uses two external pins, one input (RxCAN1) and one
output (TxCAN1). The TxCAN1 output pin represents the logic level on
the CAN: ‘0’ is for a dominant state, and ‘1’ is for a recessive state.
RxCAN1 is on bit 0 of Port CAN1, TxCAN1 is on bit 1. If the MSCAN1 is
not used, TxCAN1 should be left unconnected and, due to an internal
pull-up, the RxCAN1 pin should not be tied to VSS.
Freescale Semiconductor, Inc.
For More Information On This Product,
Pinout and Signal Descriptions
Go to: www.freescale.com
MC68HC912DT128A — Rev 4.0
Bus Control and
MOTOROLA