MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 350

• Manufacturer Part Number: MC912DG128ACPV
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128ACPV

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MSCAN Controller
18.12.4 Data Segment Registers (DSRn)
18.12.5 Transmit Buffer Priority Registers (TBPR)
Technical Data
350
1. x is 5, 6, or 7 depending on which buffer Tx0, Tx1, or Tx2 respectively.
TBPR
$01xD
RESET
(1)
W
R
NOTE:
PRIO7
BIT 7
-
The eight data segment registers contain the data to be transmitted or
being received. The number of bytes to be transmitted or being received
is determined by the data length code in the corresponding DLR.
PRIO7 – PRIO0 — Local Priority
To ensure data integrity, no registers of the transmit buffers shall be
written while the associated TXE flag is cleared.
To ensure data integrity, no registers of the receive buffer shall be read
while the RXF flag is cleared.
PRIO6
BIT 6
This field defines the local priority of the associated message buffer.
The local priority is used for the internal prioritizing process of the
msCAN12 and is defined to be highest for the smallest binary number.
The msCAN12 implements the following internal priorization
mechanism:
•
•
•
Freescale Semiconductor, Inc.
-
For More Information On This Product,
All transmission buffers with a cleared TXE flag participate in the
priorisation right before the SOF (Start of Frame) is sent.
The transmission buffer with the lowest local priority field wins the
priorisation.
In case of more than one buffer having the same lowest priority the
message buffer with the lower index number wins.
PRIO5
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BIT 5
-
MSCAN Controller
PRIO4
BIT 4
-
PRIO3
BIT 3
-
PRIO2
BIT 2
MC68HC912DT128A — Rev 4.0
-
PRIO1
BIT 1
-
MOTOROLA
PRIO0
BIT 0
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