MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 354

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MC912DG128ACPV

Manufacturer Part Number
MC912DG128ACPV
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128ACPV

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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MSCAN Controller
18.13.4 msCAN12 Bus Timing Register 0 (CBTR0)
Technical Data
354
CBTR0
$0102
RESET
W
R
NOTE:
SJW1
Bit 7
0
SJW1, SJW0 — Synchronization Jump Width
BRP5 – BRP0 — Baud Rate Prescaler
The CBTR0 register can only be written if the SFTRES bit in CMCR0 is
set.
SJW0
The synchronization jump width defines the maximum number of time
quanta (Tq) clock cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see
These bits determine the time quanta (Tq) clock, which is used to
build up the individual bit timing, according to
Freescale Semiconductor, Inc.
BRP5
6
0
For More Information On This Product,
0
0
0
0
1
:
:
SJW1
0
0
1
1
BRP4
Table
BRP5
Go to: www.freescale.com
0
0
0
0
1
:
:
5
0
Table 18-4. Synchronization jump width
MSCAN Controller
18-4).
Table 18-5. Baud rate prescaler
BRP3
0
0
0
0
1
:
:
BRP4
4
0
SJW0
0
1
0
1
BRP2
0
0
0
0
1
:
:
BRP3
3
0
BRP1
0
0
1
1
1
:
:
Synchronization jump width
BRP2
BRP0
MC68HC912DT128A — Rev 4.0
2
0
0
1
0
1
1
:
:
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
Table
Prescaler value (P)
BRP1
18-5.
1
0
64
1
2
3
4
:
:
MOTOROLA
BRP0
Bit 0
0

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