MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 288

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MC912DG128ACPV

Manufacturer Part Number
MC912DG128ACPV
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128ACPV

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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SC0SR2/SC1SR2 — SCI Status Register 2
SC0DRH/SC1DRH — SCI Data Register High
SC0DRL/SC1DRL — SCI Data Register Low
Multiple Serial Interface
Technical Data
288
RESET:
RESET:
RESET:
R7/T7
Bit 7
Bit 7
Bit 7
R8
0
0
R6/T6
T8
6
0
0
6
6
PF — Parity Error Flag
Read anytime. Write has no meaning or effect.
RAF — Receiver Active Flag
Indicates if received data’s parity matches parity bit. This feature is
active only when parity is enabled. The type of parity tested for is
determined by the PT (parity type) bit in SCxCR1.
This bit is controlled by the receiver front end. It is set during the RT1
time period of the start bit search. It is cleared when an idle state is
detected or when the receiver circuitry detects a false start bit
(generally due to noise or baud rate mismatch).
If enabled with RIE = 1, RAF set generates an interrupt when
VDDPLL is high while in WAIT mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Parity correct
1 = Incorrect parity detected
0 = A character is not being received
1 = A character is being received
R5/T5
5
0
0
5
0
5
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Multiple Serial Interface
R4/T4
4
0
0
4
0
4
R3/T3
3
0
0
3
0
3
R2/T2
2
0
0
2
0
2
MC68HC912DT128A — Rev 4.0
R1/T1
1
1
0
0
1
0
R0/T0
Bit 0
Bit 0
Bit 0
RAF
0
0
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