MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 294

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MC912DG128ACPV

Manufacturer Part Number
MC912DG128ACPV
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128ACPV

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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SP0CR1 — SPI Control Register 1
Multiple Serial Interface
16.5.4 Bidirectional Mode (MOMI or SISO)
16.5.5 Register Descriptions
Technical Data
294
RESET:
When SPE=1
Bidirectional
SPC0=0
SPC0=1
Normal
Mode
Mode
SPIE
Bit 7
0
SWOM enables open drain output. PS4 becomes GPIO.
Figure 16-6. Normal Mode and Bidirectional Mode
Serial Out
Serial Out
Serial In
Serial In
SPI
SPI
SPE
SWOM enables open drain output.
6
0
In bidirectional mode, the SPI uses only one serial data pin for external
device interface. The MSTR bit decides which pin to be used. The MOSI
pin becomes serial data I/O (MOMI) pin for the master mode, and the
MISO pin becomes serial data I/O (SISO) pin for the slave mode. The
direction of each serial I/O pin depends on the corresponding DDRS bit.
Control and data registers for the SPI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. For more information refer to
Read or write anytime.
SPIE — SPI Interrupt Enable
Freescale Semiconductor, Inc.
Master Mode
DDRS5
DDRS5
For More Information On This Product,
MSTR=1
0 = SPI interrupts are inhibited
SWOM
5
0
Go to: www.freescale.com
Multiple Serial Interface
MSTR
MOMI
4
0
PS4
MO
MI
CPOL
3
0
SWOM enables open drain output. PS5 becomes GPIO.
Serial Out
Serial Out
Serial In
Serial In
SPI
SPI
SWOM enables open drain output.
CPHA
2
1
Slave Mode
DDRS4
DDRS4
MSTR=0
MC68HC912DT128A — Rev 4.0
SSOE
1
0
Operating
LSBF
Bit 0
SISO
PS5
SO
0
SI
MOTOROLA
Modes.
$00D0

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