MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 319

• Manufacturer Part Number: MC912DG128ACPV
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128ACPV

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

17.7.2 Generation of START
17.7.3 Post-Transfer Software Response
MC68HC912DT128A — Rev 4.0
MOTOROLA
After completion of the initialization procedure, serial data can be
transmitted by selecting the 'master transmitter' mode. If the device is
connected to a multi-master bus system, the state of the IIC Bus Busy
bit (IBB) must be tested to check whether the serial bus is free.
If the bus is free (IBB=0), the start condition and the first byte (the slave
address) can be sent. The data written to the data register comprises the
slave calling address and the LSB set to indicate the direction of transfer
required from the slave.
The bus free time (i.e., the time between a STOP condition and the
following START condition) is built into the hardware that generates the
START cycle. Depending on the relative frequencies of the system clock
and the SCL period it may be necessary to wait until the IIC is busy after
writing the calling address to the IBDR before proceeding with the
following instructions. This is illustrated in the following example.
An example of a program which generates the START signal and
transmits the first byte of data (slave address) is shown below:
Transmission or reception of a byte will set the data transferring bit (TCF)
to 1, which indicates one byte communication is finished. The IIC Bus
interrupt bit (IBIF) is set also; an interrupt will be generated if the interrupt
function is enabled during initialization by setting the IBIE bit. Software
must clear the IBIF bit in the interrupt routine first. The TCF bit will be
cleared by reading from the IIC Bus Data I/O Register (IBDR) in receive
mode or writing to IBDR in transmit mode.
Software may service the IIC I/O in the main program by monitoring the
IBIF bit if the interrupt function is disabled. Note that polling should
CHFLAG
TXSTART
IBFREE
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BRSET
BSET
MOVB
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Inter IC Bus
IBSR,#$20,*
IBCR,#$30
CALLING,IBDR
IBSR,#$20,*
;WAIT FOR IBB FLAG TO CLEAR
;SET TRANSMIT AND MASTER MODE
;i.e. GENERATE START CONDITION
;TRANSMIT THE CALLING
;ADDRESS, D0=R/W
;WAIT FOR IBB FLAG TO SET
IIC Programming Examples
Technical Data
Inter IC Bus
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