MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 287

no-image

MC912DG128ACPV

Manufacturer Part Number
MC912DG128ACPV
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128ACPV

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC912DG128ACPV
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC912DG128ACPV
Manufacturer:
FREE
Quantity:
20 000
Part Number:
MC912DG128ACPV 5K91D
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC912DG128ACPVE
Manufacturer:
MICREL
Quantity:
9 982
Part Number:
MC912DG128ACPVE
Manufacturer:
FREESCALE
Quantity:
1 200
Part Number:
MC912DG128ACPVE
Manufacturer:
FREESCALE
Quantity:
1 970
Part Number:
MC912DG128ACPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC912DG128ACPVE
Manufacturer:
FREESCALE
Quantity:
1 970
Part Number:
MC912DG128ACPVER
Manufacturer:
STM
Quantity:
1 244
Part Number:
MC912DG128ACPVER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68HC912DT128A — Rev 4.0
MOTOROLA
RDRF — Receive Data Register Full Flag
IDLE — Idle Line Detected Flag
OR — Overrun Error Flag
NF — Noise Error Flag
FE — Framing Error Flag
Once cleared, IDLE is not set again until the RxD line has been active
and becomes idle again. RDRF is set if a received character is ready
to be read from SCxDR. Clear the RDRF flag by reading SCxSR1 with
RDRF set and then reading SCxDR.
Receiver idle line is detected (the receipt of a minimum of 10/11
consecutive ones). This bit will not be set by the idle line condition
when the RWU bit is set. Once cleared, IDLE will not be set again until
after RDRF has been set (after the line has been active and becomes
idle again).
New byte is ready to be transferred from the receive shift register to
the receive data register and the receive data register is already full
(RDRF bit is set). Data transfer is inhibited until this bit is cleared.
Set during the same cycle as the RDRF bit but not set in the case of
an overrun (OR).
Set when a zero is detected where a stop bit was expected. Clear the
FE flag by reading SCxSR1 with FE set and then reading SCxDR.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = SCxDR empty
1 = SCxDR full
0 = RxD line is idle
1 = RxD line is active
0 = No overrun
1 = Overrun detected
0 = Unanimous decision
1 = Noise on a valid start bit, any of the data bits, or on the stop bit
0 = Stop bit detected
1 = Zero detected rather than a stop bit
Go to: www.freescale.com
Multiple Serial Interface
Serial Communication Interface (SCI)
Multiple Serial Interface
Technical Data
287

Related parts for MC912DG128ACPV