MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 61

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MC912DG128ACPV

Manufacturer Part Number
MC912DG128ACPV
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128ACPV

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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3.5.9 Port CAN0
3.5.10 Port IB
MC68HC912DT128A — Rev 4.0
MOTOROLA
The MSCAN0 uses two external pins, one input (RxCAN0) and one
output (TxCAN0). The TxCAN0 output pin represents the logic level on
the CAN: ‘0’ is for a dominant state, and ‘1’ is for a recessive state.
RxCAN0 is on bit 0 of Port CAN0, TxCAN0 is on bit 1. If the MSCAN0 is
not used, TxCAN0 should be left unconnected and, due to an internal
pull-up, the RxCAN0 pin should not be tied to VSS.
Bidirectional pins to IIC bus interface subsystem. The IIC bus interface
uses a Serial Data line (SDA) and Serial Clock line (SCL) for data
transfer. The pins are connected to a positive voltage supply via a pull
up resistor. The pull ups can be enabled internally or connected
externally. The output stages have open drain outputs in order to
perform the wired-AND function. When the IIC is disabled the pins can
be used as general purpose I/O pins. SCL is on bit 7 of Port IB and SDA
is on bit 6. On the MC68HC912DG128A, the remaining two pins of Port
IB (PIB5 and PIB4) are controlled by registers in the IIC address space.
Register DDRIB determines pin direction of port IB when used for
general-purpose I/O. When DDRIB bits are set, the corresponding pin is
configured for output. On reset the DDRIB bits are cleared and the
corresponding pin is configured for input.
When the PUPIB bit in the IBPURD register is set, all input pins are
pulled up internally by an active pull-up device. Pullups are disabled after
reset, except for input ports 0 through 5, which are always on regardless
of PUPIB bit.
Setting the RDPIB bit in the IBPURD register configures all port IB
outputs to have reduced drive levels. Levels are at normal drive
capability after reset. The IBPURD register can be read or written
anytime after reset. Refer to section
Freescale Semiconductor, Inc.
For More Information On This Product,
Pinout and Signal Descriptions
Go to: www.freescale.com
Inter IC
Bus.
Pinout and Signal Descriptions
Technical Data
Port Signals
61

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