MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 155

IC MCU 128K FLASH 25MHZ 80-QFP

MC9S12E128CFU

Manufacturer Part Number
MC9S12E128CFU
Description
IC MCU 128K FLASH 25MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CFU

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
60
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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3.3.7
Port U is associated with one 4-channel timer (TIM2) and the pulse width modulator (PWM) module. Each
pin is assigned to these modules according to the following priority: TIM2/PWM > general-purpose I/O.
If the timer TIM2 is enabled, the channels configured for output compare are available on port U pins
PU[3:0]. Refer to the TIM block description chapter for information on enabling and disabling the TIM
module.
When a PWM channel is enabled, the corresponding pin becomes a PWM output. Refer to the PWM block
description chapter for information on enabling and disabling the PWM channels.
If both PWM and TIM2 are enabled simultaneously, the pin functionality is determined by the
configuration of the MODRR bits
During reset, port U pins are configured as high-impedance inputs.
3.3.7.1
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRUx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRUx) is set to 0 (input), a read returns the value of the pin.
3.3.7.2
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
Freescale Semiconductor
PWM:
Reset
Reset
TIM2:
W
W
R
R
PTIU7
Port U
PTU7
Port U I/O Register (PTU)
Port U Input Register (PTIU)
0
u
7
7
= Reserved or Unimplemented
PTIU6
PTU6
0
u
6
6
Figure 3-43. Port U Input Register (PTIU)
Figure 3-42. Port U I/O Register (PTU)
PTIU5
PTU5
PW15
MC9S12E128 Data Sheet, Rev. 1.07
0
u
5
5
PTIU4
PTU4
PW14
0
u
4
4
u = Unaffected by reset
PTIU3
PTU3
PW13
OC27
0
u
3
3
Chapter 3 Port Integration Module (PIM9E128V1)
PTIU2
PTU2
PW12
OC26
0
u
2
2
PTIU1
PTU1
PW11
OC25
0
u
1
1
PTIU0
PTU0
PW10
OC24
0
u
0
0
155

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