MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 335

• Manufacturer Part Number: MC9S12E128CFU
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

11.3.2.5
Read and write anytime.
11.3.2.6
Read anytime. This register cannot be modified after the WP bit is set.
Freescale Semiconductor
FMODE[3:0]
Module Base + 0x0004
Module Base + 0x0005
FPINE[2:0]
7, 5, 3, 1
6, 4, 2, 0
6, 4, 2, 0
FIE[3:0]
Reset
Reset
Field
Field
W
W
R
R
FMODE3
Fault x Pin Clearing Mode — This bit selects automatic or manual clearing of FAULTx pin faults. See
Section 11.4.8.2, “Automatic Fault Clearing”
0 Manual fault clearing of FAULTx pin faults.
1 Automatic fault clearing of FAULTx pin faults.
where x is 0, 1, 2, and 3.
Fault x Pin Interrupt Enable — This bit enables CPU interrupt requests to be generated by the FAULTx pin. The
fault protection circuit is independent of the FIEx bit and is active when FPINEx is set. If a fault is detected, the
PWM pins are disabled according to the PMF Disable Mapping registers.
0 Fault x CPU interrupt requests disabled.
1 Fault x CPU interrupt requests enabled.
where x is 0, 1, 2 and 3.
Fault x Pin Enable — Where x is 0, 1, 2 and 3.
0 FAULTx pin is disabled for fault protection.
1 FAULTx pin is enabled for fault protection.
PMF Fault Control Register (PMFFCTL)
PMF Fault Pin Enable Register (PMFFPIN)
0
0
0
7
7
= Unimplemented or Reserved
FPINE3
FIE3
Figure 11-9. PMF Fault Pin Enable Register (PMFFPIN)
0
0
6
6
Figure 11-8. PMF Fault Control Register (PMFFCTL))
Table 11-6. PMFFCTL Field Descriptions
Table 11-7. PMFFPIN Field Descriptions
FMODE2
MC9S12E128 Data Sheet, Rev. 1.07
0
0
0
5
5
FPINE2
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
FIE2
and
0
0
4
4
Section 11.4.8.3, “Manual Fault Clearing”
Description
Description
FMODE1
0
0
0
3
3
FPINE1
FIE1
0
0
2
2
FMODE0
0
0
0
1
1
for more details.
FPINE0
FIE0
0
0
0
0
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