MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 75

IC MCU 128K FLASH 25MHZ 80-QFP

MC9S12E128CFU

Manufacturer Part Number
MC9S12E128CFU
Description
IC MCU 128K FLASH 25MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CFU

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
60
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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1.6
1.6.1
Eight possible modes determine the operating configuration of the MC9S12E128. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
1.6.2
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and
provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are
latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the
ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map.
ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into
the ROMON bit in the MISC register on the rising edge of the reset signal.
For further explanation on the modes refer to the HCS12 MEBI block description chapter.
Freescale Semiconductor
BKGD =
MODC
0
0
0
0
1
1
1
1
Modes of Operation
Overview
Chip Configuration Summary
MODB
PE6 =
0
0
1
1
0
0
1
1
PE7 = XCLKS
MODA
PE5 =
0
1
0
1
0
1
0
1
1
0
Table 1-8. Clock Selection Based on PE7
ROMCTL
PK7 =
MC9S12E128 Data Sheet, Rev. 1.07
X
X
X
X
Colpitts Oscillator selected
Pierce Oscillator/external clock selected
0
1
0
1
0
1
0
1
Table 1-7. Mode Selection
ROMON
Bit
1
1
0
0
1
0
1
0
1
1
0
1
Description
Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1)
Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Peripheral; BDM allowed but bus operations would cause
bus conflicts (must not be used)
Normal Expanded Wide, BDM allowed
Mode Description
75

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