MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 93

• Manufacturer Part Number: MC9S12E128CFU
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

2.3.2.4
The FCNFG register enables the Flash interrupts and gates the security backdoor key writes.
CBEIE, CCIE, and KEYACC are readable and writable while remaining bits read 0 and are not writable.
KEYACC is only writable if the KEYEN bit in the FSEC register is set to the enabled state (see
2.3.2.2).
2.3.2.5
The FPROT register defines which Flash sectors are protected against program or erase.
The FPROT register is readable in normal and special modes. FPOPEN can only be written from a 1 to a 0.
FPLS[1:0] can be written anytime until FPLDIS is cleared. FPHS[1:0] can be written anytime until
Freescale Semiconductor
Module Base + 0x0003
Module Base + 0x0004
KEYACC
Reset
CBEIE
Reset
Field
CCIE
7
6
5
W
W
R
R
FPOPEN
CBEIE
Command Buffer Empty Interrupt Enable — The CBEIE bit enables the interrupts in case of an empty
command buffer in the Flash module.
0 Command Buffer Empty interrupts disabled
1 An interrupt will be requested whenever the CBEIF flag is set (see
Command Complete Interrupt Enable — The CCIE bit enables the interrupts in case of all commands being
completed in the Flash module.
0 Command Complete interrupts disabled
1 An interrupt will be requested whenever the CCIF flag is set (see
Enable Security Key Writing.
0 Flash writes are interpreted as the start of a command write sequence
1 Writes to the Flash array are interpreted as a backdoor key while reads of the Flash array return invalid data
Flash Configuration Register (FCNFG)
Flash Protection Register (FPROT)
F
0
7
7
= Unimplemented or Reserved
CCIE
NV6
0
F
6
6
Figure 2-7. Flash Configuration Register (FCNFG)
Figure 2-8. Flash Protection Register (FPROT)
Table 2-7. FCNFG Field Descriptions
KEYACC
FPHDIS
MC9S12E128 Data Sheet, Rev. 1.07
0
F
5
5
FPHS1
0
0
F
4
4
Description
FPHS0
F
0
0
3
3
Chapter 2 128 Kbyte Flash Module (FTS128K1V1)
Section
Section
FPLDIS
0
0
F
2
2
2.3.2.6)
2.3.2.6)
FPLS1
0
0
F
1
1
Section
FPLS0
F
0
0
0
0
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