MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 337

• Manufacturer Part Number: MC9S12E128CFU
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

11.3.2.9
Read anytime. These registers cannot be modified after the WP bit is set.
Freescale Semiconductor
Module Base + 0x0008
Module Base + 0x0009
Module Base + 0x000A
DMP[00:53]
Reset
Reset
Reset
Field
7–0
W
W
W
R
R
R
DMP13
DMP33
DMP53
PMF Disable Mapping Bits — The fault decoder disables PWM pins selected by the fault logic and the disable
mapping registers. See
of a single PWM pin. Refer to
PMF Disable Mapping Registers
0
0
0
7
7
7
Table 11-11. PMFDMPA, PMFDMPB, and PMFDMPC Field Descriptions
Figure 11-13. PMF Disable Mapping B Register (PMFDMPB)
Figure 11-14. PMF Disable Mapping C Register (PMFDMPC)
DMP12
Figure 11-12. PMF Disable Mapping A Register (PMFDMPA)
DMP32
DMP52
0
0
0
6
6
6
1
There is an asynchronous path from fault pin to disable
PWMs immediately but the fault is qualified in two bus
cycles.
QSMPx
Figure
00
01
10
11
DMP11
DMP31
DMP51
Table 11-10. Qualifying Samples
MC9S12E128 Data Sheet, Rev. 1.07
Table
11-15. Each bank of four bits in the disable mapping registers control the mapping
0
0
0
5
5
5
11-12.
DMP10
DMP30
DMP50
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
0
0
0
4
4
4
Number of Samples
Description
10 samples
15 samples
5 samples
1 sample
DMP03
DMP23
DMP43
0
0
0
3
3
3
1
DMP02
DMP22
DMP42
0
0
0
2
2
2
DMP01
DMP21
DMP41
0
0
0
1
1
1
DMP00
DMP20
DMP40
0
0
0
0
0
0
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