MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 373

• Manufacturer Part Number: MC9S12E128CFU
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

11.4.7
11.4.7.1
The load okay bit, LDOK, enables loading the PWM generator with:
LDOK prevents reloading of these PWM parameters before software is finished calculating them Setting
LDOK allows the prescaler bits, PMFMOD and PMFVALx registers to be loaded into a set of buffers. The
loaded buffers use the PWM generator at the beginning of the next PWM reload cycle. Set LDOK by
reading it when it is a logic zero and then writing a logic one to it. After loading, LDOK is automatically
cleared.
11.4.7.2
The LDFQ3, LDFQ2, LDFQ1, and LDFQ0 bits in the PWM control register (PWMCTL) select an integral
loading frequency of one to 16-PWM reload opportunities. The LDFQ bits take effect at every PWM
reload opportunity, regardless the state of the load okay bit, LDOK. The half bit in the PWMCTL register
controls half-cycle reloads for center-aligned PWMs. If the half bit is set, a reload opportunity occurs at
the beginning of every PWM cycle and half cycle when the count equals the modulus. If the half bit is not
set, a reload opportunity occurs only at the beginning of every cycle. Reload opportunities can only occur
at the beginning of a PWM cycle in edge-aligned mode.
Freescale Semiconductor
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•
•
A prescaler divisor—from the PRSC1 and PRSC0 bits in PWM control register
A PWM period—from the PWM counter modulus registers
A PWM pulse width—from the PWM value registers
FREQUENCY
COUNTER
UP/DOWN
PWM Generator Loading
CHANGE
FREQUENCY
RELOAD
RELOAD
Load Enable
Load Frequency
COUNTER
Loading a new modulus on a half cycle will force the count to the new
modulus value minus one on the next clock cycle. Half cycle reloads are
possible only in center-aligned mode. Enabling or disabling half-cycle
reloads in edge-aligned mode will have no effect on the reload rate.
UP/DOWN
CHANGE
RELOAD
RELOAD
TWO OPPORTUNITIES
Figure 11-66. Half Cycle Reload Frequency Change
Figure 11-65. Full Cycle Reload Frequency Change
TO EVERY
TWO OPPORTUNITIES
TO EVERY
MC9S12E128 Data Sheet, Rev. 1.07
FOUR OPPORTUNITIES
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
NOTE
TO EVERY
FOUR OPPORTUNITIES
TO EVERY
OPPORTUNITY
TO EVERY
TWO OPPORTUNITIES
OPPORTUNITY
TO EVERY
TO EVERY
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