MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 346

• Manufacturer Part Number: MC9S12E128CFU
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
11.3.2.21 PMF Frequency Control A Register (PMFFQCA)
Read and write anytime.
346
Module Base + 0x0021
PWMRFA
PRSCA
LDFQA
HALFA
Reset
Field
7–4
2–1
3
0
W
R
LDFQA
0000
0001
0010
0011
0100
0101
0110
0111
Load Frequency A — This field selects the PWM load frequency according to
Section 11.4.7.2, “Load Frequency”
Note: The LDFQA field takes effect when the current load cycle is complete, regardless of the state of the load
Half Cycle Reload A — This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect
on edge-aligned PWMs.
0 Half-cycle reloads disabled
1 Half-cycle reloads enabled
Prescaler A — This buffered field selects the PWM clock frequency illustrated in
Note: Reading the PRSCA field reads the buffered value and not necessarily the value currently in effect. The
PWM Reload Flag A — This flag is set at the beginning of every reload cycle regardless of the state of the
LDOKA bit. Clear PWMRFA by reading PMFFQCA with PWMRFA set and then writing a logic one to the
PWMRFA bit. If another reload occurs before the clearing sequence is complete, writing logic one to PWMRFA
has no effect.
0 No new reload cycle since last PWMRFA clearing
1 New reload cycle since last PWMRFA clearing
Note: Clearing PWMRFA satisfies pending PWMRFA CPU interrupt requests.
0
7
okay bit, LDOKA. Reading the LDFQA field reads the buffered value and not necessarily the value
currently in effect.
PRSCA field takes effect at the beginning of the next PWM cycle and only when the load okay bit, LDOKA,
is set.
Figure 11-27. PMF Frequency Control A Register (PMFFQCA)
Every 2 PWM opportunities
Every 3 PWM opportunities
Every 4 PWM opportunities
Every 5 PWM opportunities
Every 6 PWM opportunities
Every 7 PWM opportunities
Every 8 PWM opportunities
0
6
PWM Reload Frequency
Every PWM opportunity
LDFQA
Table 11-26. PMFFQCA Field Descriptions
Table 11-27. PWM Reload Frequency A
MC9S12E128 Data Sheet, Rev. 1.07
0
5
for more details.
0
4
Description
LDFQ[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
HALFA
0
3
Every 10 PWM opportunities
Every 11 PWM opportunities
Every 12 PWM opportunities
Every 13 PWM opportunities
Every 14 PWM opportunities
Every 15 PWM opportunities
Every 16 PWM opportunities
Every 9 PWM opportunities
PWM Reload Frequency
0
2
PRSCA
Table
Table
11-27. See
Freescale Semiconductor
11-28.
0
1
PWMRFA
0
0