MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 64

• Manufacturer Part Number: MC9S12E128CFU
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1)
1.4
1.4.1
EXTAL and XTAL are the external clock and crystal driver pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
1.4.2
RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known
start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in
either the clock monitor or COP watchdog circuit. External circuitry connected to the RESET pin should
not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one
within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit
drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal
processing.
1.4.3
The TEST pin is reserved for test and must be tied to VSS in all applications.
1.4.4
Dedicated pin used to create the PLL loop filter. See the CRG block description chapter for more detailed
information.
1.4.5
The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug
communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched
to the MODC bit at the rising edge of RESET. In MCU expanded modes of operation, when instruction
tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction
word being read into the instruction queue. This pin always has an internal pull up.
1.4.6
PA[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. PA[7:0] pins are not available in the 80 pin package
version.
1.4.7
PB[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. PB[7:0] pins are not available in the 80 pin package
version.
64
Detailed Signal Descriptions
EXTAL, XTAL — Oscillator Pins
RESET — External Reset Pin
TEST — Test Pin
XFC — PLL Loop Filter Pin
BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin
PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor