MC9S12E128CFU Freescale Semiconductor, MC9S12E128CFU Datasheet - Page 195

• Manufacturer Part Number: MC9S12E128CFU
• Description: IC MCU 128K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CFU

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Freescale Semiconductor
CME
0
1
1
SCME
X
0
1
SCMIE
X
X
0
Clock failure -->
Clock failure -->
Clock Monitor failure -->
Scenario 1: OSCCLK recovers prior to exiting Pseudo-Stop Mode.
Scenario 2: OSCCLK does not recover prior to exiting Pseudo-Stop Mode.
Table 4-12. Outcome of Clock Loss in Pseudo-Stop Mode
No action, clock loss not detected.
CRG performs Clock Monitor Reset immediately
– MCU remains in Pseudo-Stop Mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start Clock Quality Check,
– Set SCMIF interrupt flag.
Some time later OSCCLK recovers.
– CM no longer indicates a failure,
– 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k.,
– SCM deactivated,
– PLL disabled,
– VREG disabled.
– MCU remains in Pseudo-Stop Mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
– Exit Pseudo-Stop Mode using OSCCLK as system clock (SYSCLK),
– Continue normal operation.
– Exit Pseudo-Stop Mode using OSCCLK as system clock,
– Start reset sequence.
– MCU remains in Pseudo-Stop Mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start Clock Quality Check,
– Set SCMIF interrupt flag,
– Keep performing Clock Quality Checks (could continue infinitely)
Some time later either a wakeup interrupt occurs (no SCM interrupt)
– Exit Pseudo-Stop Mode in SCM using PLL clock (f
– Continue to perform additional Clock Quality Checks until OSCCLK
or an External RESET is applied.
– Exit Pseudo-Stop Mode in SCM using PLL clock (f
– Start reset sequence,
– Continue to perform additional Clock Quality Checks until OSCCLK
or an External Reset is applied.
is o.k. again.
is o.k.again.
while in Pseudo-Stop Mode.
MC9S12E128 Data Sheet, Rev. 1.07
CRG Actions
Chapter 4 Clocks and Reset Generator (CRGV4)
SCM
SCM
) as system clock
) as system clock
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